1. Field of the Invention
The present invention relates generally to computer memory storage and more particularly to storing modeling data in computer memory.
2. Description of Related Art
Simulations of Very High Speed Integrated Circuit (VHSIC) designs require the use of Hardware Description Languages (HDL's) such as VHDL (VHSIC Hardware Description Language) to model the behavior of hardware components. One class of components that is frequently modeled is memory devices. The memory devices include, for example: random access memory devices (RAM), read-only memory devices (ROM), and electrically erasable read only memory devices (EEPROM).
Existing VHDL memory models use an array of standard logic vector (std.sub.-- logic.sub.-- vector) variables to represent memory modeling data. For a description of std.sub.-- logic.sub.-- vector variable formats, see the following reference: IEEE STD 1164-1993 "IEEE Standard Multivalue Logic System for VHDL Model Interoperability (std.sub.-- logic.sub.-- 1164)." The std logic.sub.-- vector format requires approximately anywhere from eight bytes to eleven bytes to represent one byte of modeled memory. Consequently, a 64 megabyte (Mbyte) memory model may require as much as 704 Mbytes of workstation memory.
This large memory storage requirement mandates the use of workstations with large memory storage capacities. Moreover, the storage requirement significantly slows down the simulation program since, among other reasons, swapping may be required if the workstation is not capable of holding the entire simulation data in the workstation's available RAM. Hardware accelerators can be used to speed up the simulation. However, hardware accelerators are relatively expensive and may cost more than $2 million for one accelerator.